This invention relates to the use of digital shift registers for the storage of digital information and more particularly to the storage of video signals in digital television equipment. The conversion of analogue video signals to digital form and the control for writing in of the digital signals into storage means (e.g. shift registers) and the subsequent reading out of the digital information from the store is known for example from U.S. Pat Nos. 3,860,952; 3,752,912; 3,830,971. When handling a television signal in digital form it is common practice to sample the analogue video signal for conversion to the digital format at a rate, at or near, three times the colour sub carrier frequency. This choice of sampling frequency satisfies the requirements of sampling theory and minimizes the visibility of spurious patterns produced by the sampling process. Having made this choice of sampling rate, the word rate of the digital code describing the television signal is fixed as are the parameters of the television system itself. The active picture period of each television scanning line is therefore sub divided into a minimum number of digital words sufficient to embrace the information period. In the case of an American NTSC colour television signal having an active line period of 53.5 microseconds and a colour sub carrier frequency of 3.58 MHz, the minimum number of words per active line = 53.5 microseconds times 10.7 MHz, i.e. 575 words.
Where digital shift registers are used to store a television signal in increments of one scanning line duration, it is necessary to choose components which have sufficient capacity, i.e. the correct length in the case of shift registers, and also an adequate operating speed. Currently available large scale integrated circuit shift registers have a limited operating speed which requires that the 10.7 MHz word rate be demultiplexed by a factor of 2, 3 or more, to reduce the rate at which the shift register must be clocked. If, for example, the digital word rate is demultiplexed by a factor of 3, then every third word is allocated to one of three parallel shift registers each with a length one third of the total required. If in the example taken the number of words per active line is rounded up to the nearest whole number divisible by three, 576 words, then the shift register length required in each of three parallel demultiplexed paths is 192. This length of 192 can be assembled for each register from three separate 64 bit shift registers in cascade. 64 happens to be one of a number of commonly available shift register lengths. Therefore, a system using a demultiplexing factor of three and registers of length 192 would require a total of nine registers of 64 bit length for each bit of the digital word. If for example the word comprises: 8 bits (in parallel form), then 8 register arrangements as described above will be required. The number of 64 bit registers will be 9 .times. 8 = 72. So, in view of the relatively small size of the 64 bit register, a more economic solution is required.